1. Field
Exemplary embodiments of the present invention relate to a parity check circuit and a memory device including the same.
2. Description of the Related Art
A parity check is a technology for checking whether data has been lost or damaged during transmission. There are multiple different types of parity check methods being used in the verification of data transmission. In addition, n-out-of-r code (nCr) methods and cyclic redundancy check (CRC) methods are also used to verify the transmission of data.
In a parity check, the number of bits of received multi-bit data that have a value of “1” is set as an even (or odd) number. Therefore, an error in the received data may be detected by checking whether the received data have an even (or odd) number of bits with a value of “1”. For example, in an even parity check, if the number of bits of received multi-bit data that have a value of “1” is an even number, it means no errors should be present. If the number of bits having a value of “1” is odd, this means there is an error. In contrast, in an odd parity check, if the number of bits of received multi-bit data that have a value of “1” is an odd number, there should not be any errors. If there is an even number of bits with a value of “1”, an error has occurred.
In accordance with the JEDEC specs for DDR4 SDRAM, now being discussed in the industry, a function for performing a parity check using a command and an address applied to a memory device and sending information about the command to a memory controller if an error is detected in the command is defined. The memory controller may stop operations subsequent to the command, that is, operations after an error occurs, based on transmitted detection information.
For a parity check, parity data combined through exclusive OR (hereinafter referred to as XOR) for all the bits of data to be checked may be generated. If there are a lot data bits to be checked, parity data needs to be generated by connecting multi-stage XOR gates. An XOR gate has asynchronous delay and is problematic in that it may generate data errors or cause difficulty in setting the timing of a parity check operation accurately.